DFT Intern

Job Description

DFT Intern | Etched

The Tone:
This is a paid internship at Etched, located in San Jose, CA. Etched is a company dedicated to building hardware for frontier intelligence, focusing on the co-design of chips, racks, software, and manufacturing to achieve best-in-class throughput and latency, particularly for inference workloads. The DFT Intern role is crucial for ensuring the reliability and testability of these advanced chips, directly contributing to the foundational infrastructure for the fastest-growing industry in history.

The TL;DR
• Role: Internship
• Type: Seasonal
• Location: In-person, San Jose, CA
• Team: Will collaborate across frontend and backend design teams, receiving direct mentorship from industry leaders and engineers.
• Mission: Help refine DFT flow automation and contribute to chip-level regression and verification, ensuring the testability and reliability of high-performance AI chips.
• Tech Stack: Verilog, SystemVerilog, Python, Tcl, Tessent

What You’ll Actually Do
• Automation Review: Help review and refine existing DFT flow automation processes to enhance efficiency and coverage.
• Regression Support: Support chip-level regression activities on the Caelius chip, ensuring robust testing and validation of the hardware.
• Team Collaboration: Work collaboratively across both frontend and backend design teams to integrate and verify comprehensive DFT solutions effectively.
• DFT Verification: Contribute to essential DFT verification tasks, which include conducting simulations for MBIST, Scan, BSCAN, and SSN.
• Flow Development: Develop new flows for various ATPG fault models, such as Stuck-At Fault (SAF), Transition Delay Fault (TDF), Bridge Fault (BDF), IDDQ, and Pattern-Dependent Fault (PDF).

The Must-Haves
• Background: Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a closely related technical field.
• Experience: Exposure to fundamental ASIC or SoC design concepts and familiarity with standard ASIC design flow steps, including synthesis, static timing analysis (STA), and design-for-test (DFT).
• Skills: Familiarity with a hardware description language like Verilog or SystemVerilog, a solid understanding of digital logic design fundamentals, and proficiency in scripting languages such as Python or Tcl. The ability to learn quickly about transformers and other aspects of modern artificial intelligence is also expected.
• Bonus: Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression; practical experience with Tessent or comparable DFT tooling; familiarity with various ATPG fault models (SAF, TDF, BDF, IDDQ, PDF); exposure to DFT flow automation or regression infrastructure; and familiarity with clocking and reset schemes.