SoC Power and Performance Lead, TPU
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Job Description
About Google’s Technical Infrastructure Team
The Technical Infrastructure team at Google is responsible for building and maintaining the infrastructure that powers all of Google’s online products. This team is comprised of engineers who develop and maintain data centers, build new Google platforms, and ensure the best user experience possible. They are responsible for keeping Google’s network up and running, ensuring users have the fastest and most reliable experience.
About the SoC Power and Performance Lead Role
This role is part of a diverse team developing custom silicon solutions for Google’s direct-to-consumer products. You will contribute to the innovation behind products used by millions worldwide, shaping the next generation of hardware experiences and delivering unparalleled performance, efficiency, and integration.
Specifically, you will:
• Be part of a team developing next-generation AI accelerators for data centers.
• Have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation.
• Play a vital role in shaping the future of data centers, as power and performance are key focus areas.
Responsibilities
• Lead all aspects of power definition and implementation for AI/ML SoCs: This includes defining and implementing power strategies for the chip, collaborating with other teams to ensure efficient power usage, and ensuring the chip meets its performance targets.
• Collaborate with the architecture team on power-performance trade-off analysis as part of product definition: This involves analyzing the trade-offs between power consumption and performance, and making recommendations for the chip’s design based on these analyses.
• Drive power management and power delivery schemes, power rail definitions, and implementation strategies working closely with platform and package teams: This involves working with teams that design the chip’s platform and packaging to ensure that the chip is powered efficiently and reliably.
• Model power envelopes at various workloads and performance points: This involves creating models of the chip’s power consumption at different workloads and performance levels, to help predict the chip’s power usage in real-world scenarios.
• Drive power estimation, modeling, power roll ups, and pre silicon and post silicon correlation: This involves ensuring that the chip’s power consumption is accurately estimated and modeled, and that these estimates are validated in both pre-silicon and post-silicon testing.
Minimum Qualifications
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in development of complex ASICs.
• 8 years of experience in architecture, micro-architecture, and design of ASICs/SoCs.
• Experience defining and driving power management and power delivery strategies.
• Experience in power modeling and driving low power implementations.
Preferred Qualifications
• Experience with performance modeling tools.
• Knowledge of accelerator architectures and data center workloads.
• Knowledge of high performance and low power design techniques.
