Verification Architect/ Engineer

Job Description

Infra DV Staff Engineer | Qualcomm

The Tone:
This is a full-time role at Qualcomm India Private Limited, located in India. Qualcomm is a leading technology innovator, pushing the boundaries of what’s possible to enable next-generation experiences and driving digital transformation for a smarter, connected future. This role is crucial for verifying the infrastructure IPs that go into cutting-edge System-on-Chips for products like smartphones and tablets, ensuring robust performance and quality.

The TL;DR
• Role: Staff Engineer
• Type: Full-time
• Location: In-person, India

• Team: Hardware Engineering within the broader Engineering Group
• Mission: Responsible for the verification of next-generation Infrastructure IPs, ensuring their quality and functionality for System-on-Chip products.
• Tech Stack: UVM, System Verilog, Python, Perl, C/C++/SystemC, Certitude, VC Formal, VPlan

What You’ll Actually Do
• Ownership: Own the development and maintenance of the DV test bench and associated collaterals, including Checkers, Trackers, Scoreboards, Assertions, and Functional Coverage.
• Test Development: Develop comprehensive test plans and test cases to thoroughly cover the design feature set and drive functional and code coverage closure across different test bench levels.
• Collaboration: Collaborate closely with System Architects, Design, and Emulation teams for failure debugs and to ensure complete code and functional coverage closure.
• Debugging: Debug regression signatures and identify necessary bug fixes to maintain system stability and performance.
• Post-Silicon Support: Debug and root cause post-silicon issues in collaboration with Design, Software, and Test teams.

The Must-Haves
• Background: Staff Engineer level, holding a Bachelor’s, Master’s, or PhD degree in Electrical/Electronics Engineering, Computer Science, or a related engineering field, specializing in Hardware Engineering and IP verification.
• Experience: A minimum of 4+ years in Hardware Engineering or related work experience (or 3+ years with a Master’s, 2+ years with a PhD), including at least 3 years specifically in IP verification or a related field.
• Skills: Strong debugging, analytical, and problem-solving abilities; Expertise in UVM-based verification; Knowledgeable about ARM bus protocols, Virtual Memory concepts, and SoC system architecture; Experience in developing Monitors, Scoreboards, and Sequencers using System Verilog, UVM, and scripting.
• Bonus: Experience with designs optimized for low power (e.g., dynamic clock gating, logic/memory power collapse); Experience verifying designs to Automotive Safety Integrity Levels (ASIL); Proficiency in scripting languages such as Python or Perl for automation initiatives; Experience with C/C++/SystemC for performance models; Post-silicon bring-up and hardware-software debug experience; Knowledge and exposure to silicon debug tool chains.