Verification Architect/ Engineer

Job Description

NOC DV Staff Engineer | Qualcomm

The Tone:
This is a full-time role at Qualcomm, located in Karnataka, India. Qualcomm is a leading technology innovator, constantly pushing boundaries to enable next-generation experiences and drive digital transformation. This role is crucial for verifying the next-generation infrastructure IPs that are fundamental to Qualcomm’s System-on-chip (SoC) products, ensuring the quality and performance of devices like smartphones and tablets. You will play a key part in designing, optimizing, and verifying the electronic systems that launch cutting-edge, world-class products.

The TL;DR
• Role: Full Time
• Type: Full-time
• Location: In-person, Karnataka, India

• Mission: Responsible for the verification of next-generation Infrastructure IPs for System-on-chip (SoC) products in various product categories.
• Tech Stack: UVM, System Verilog, ARM bus protocols, Python, Perl, C/C++/SystemC, Certitude, VC Formal, VPlan

What You’ll Actually Do
• Ownership: Own the development and maintenance of the DV test bench and associated collateral, including checkers, trackers, scoreboards, assertions, and functional coverage.
• Development: Develop comprehensive test plans and test cases to thoroughly cover design feature sets and drive functional and code coverage closure.
• Collaboration: Work closely with System Architects, Design, and emulation teams to debug failures and achieve verification coverage goals throughout the IP development cycle.
• Debugging: Debug regression signatures to identify root causes and implement necessary bug fixes.
• Quality Assurance: Take responsibility for quality sign-off and prepare all required documentation for the IP verification process.
• Post-Silicon Support: Debug and root cause post-silicon issues in collaboration with Design, Software, and test teams.

The Must-Haves
• Background: Senior-level Hardware Verification Engineer with a Bachelor’s or Master’s degree in Electronics & Communication, Micro Electronics, Computer Science, Electrical/Electronics Engineering, or a related engineering field.
• Experience: 8+ years of dedicated experience in IP verification or related work, demonstrating expertise in verifying complex digital designs. Specific experience with UVM-based verification methodologies and ARM Bus protocols is essential.
• Skills: Strong debugging, analytical, and problem-solving skills; Expertise in UVM-based verification; Deep knowledge of ARM bus protocols, Virtual Memory concepts, and SoC system architecture; Experience developing monitors, scoreboards, and sequencers utilizing System Verilog, UVM, and scripting; Excellent communication and collaboration skills to work effectively within a large, worldwide design organization.
• Bonus: Experience in designing or verifying designs optimized for low power, such as dynamic clock gating and logic/memory power collapse; Experience verifying designs meeting Automotive Safety Integrity Levels (ASIL); Proficiency in scripting languages like Python or Perl for automation initiatives, and C/C++/SystemC for performance models; Post-silicon bring-up and hardware-software debug experience, along with knowledge and exposure to silicon debug tool chains.