Digital RTL Verification Engineer – SoC Verification

Job Description

ASIC Verification EEJ 2026 | Bosch

The Tone:
This is a full-time role at Bosch, contributing to the development of highly advanced automotive ASICs. The company is at the forefront of creating sophisticated integrated circuits that are essential for the next generation of vehicle systems. This position is critical for ensuring the absolute reliability, functionality, and performance of these complex hardware components through meticulous verification processes, directly impacting the safety and innovation of future automotive technology.

The TL;DR
• Role: Experienced Professional
• Type: Full-time
• Location: In-person
• Mission: Verify complex automotive ASICs, SoCs, subsystems, and intellectual properties with high precision to ensure robust functionality and quality for advanced vehicle systems.
• Tech Stack: System Verilog, UVM, OVM, Cadence tools, Synopsys tools, Mentor tools, Perl, TCL

What You’ll Actually Do
• Conduct Verification: Perform comprehensive verification of SoCs, critical automotive ASICs, various subsystems, and individual IPs to meet stringent quality standards.
• Apply Methodologies: Apply advanced Metric-driven Verification (MDV) and/or Formal Verification methodologies to thoroughly test designs.
• Build Environments & IPs: Develop robust verification environments from the ground up, which includes creating new Verification IPs (VIPs) and integrating existing ones.
• Plan, Track & Analyze: Develop and meticulously track detailed verification plans, then measure and analyze regression results to identify issues and ensure design robustness.
• Drive Improvement: Work actively with Electronic Design Automation (EDA) partners to continuously improve verification methods, tools, flows, and overall processes.

The Must-Haves
• Background: This is a role for an experienced professional, requiring a Bachelor’s (BE/B.Tech) or Master’s (ME/M.Tech) degree in Electronics and Communication.
• Experience: Candidates must possess 5 to 10 years of dedicated experience in Digital RTL verification utilizing System Verilog and UVM. A critical requirement is having been a key contributor to at least one ASIC or SoC tape-out project.
• Skills: Core skills include sound knowledge of constrained random verification, UVM/OVM, and System Verilog. Expertise in developing functional coverage code and performing coverage analysis is essential, alongside good hands-on experience with industry-standard Cadence, Synopsys, or Mentor tools. Familiarity with configuration management and bug tracking tools is also required, coupled with knowledge of scripting languages such as Perl and TCL, and good experience with AMBA protocols.
• Bonus: Desirable qualifications include prior experience with Formal verification, working knowledge of ARM processor-based subsystem/SoC verification, and familiarity with VHDL/VERILOG. Knowledge of SPECMAN is also a plus.