Pre-Si Validation Engineer
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Description
About Intel
Intel is a world leader in computing innovation. We design and build the essential technologies that serve as the foundation for the world’s computing devices and intelligent devices. We empower businesses and individuals to unlock their potential and shape the future of technology.
Description
Pre-Si Validation Engineer
The Pre-Si Validation Engineer is responsible for performing functional verification of IP logic to ensure that the design meets specification requirements. This role develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. The Pre-Si Validation Engineer executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. This role replicates, root causes, and debugs issues in the presilicon environment. The Pre-Si Validation Engineer finds and implements corrective measures to resolve failing tests. This role collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. The Pre-Si Validation Engineer documents test plans and drives technical reviews of plans and proofs with design and architecture teams. This role maintains and improves existing functional verification infrastructure and methodology. The Pre-Si Validation Engineer participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Currently pursuings
• Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than 8 years of relevant industry experience out of which at least 6 years of hands-on IP verification experience using SV and UVM
• Proficiency in SV, UVM, and object-oriented programming
• Strong understanding of verification principles
• Proven track record in IP verification from environment development to tests development to validation closure
• Excellent written and verbal communication skills
• Very good at creation of test plans schedules and cost estimates for design verification efforts
• Experience in the development and deployment of verification strategies and methodologies across teams and organizations is added advantage
• Apart from simulation should have work experience with at least one other verification aspect like formal verification, gate Level verification, etc.
• Knowledge of Ethernet, PCI, USB, I3C, SPI, IOSF, AXI, DMAs, Mailboxes; will be added advantage.
• Proficiency in scripting languages and utilities including Make Perl Python etc.
• Expert-level knowledge of simulation tools such as VCS from Synopsys.
