Physical Design Intern

Job Description

Physical Design Intern | Etched

The Tone:
This is an internship at Etched, located in San Jose, CA. Etched is developing the world’s first AI inference system specifically designed for transformers, targeting over 10 times higher performance, significantly lower cost, and reduced latency compared to current B200 GPUs. This role is essential for transforming front-end designs into functional silicon, directly contributing to the acceleration of development and iteration speed for groundbreaking AI infrastructure. Your work will enable the creation of applications like real-time video generation and advanced chain-of-thought reasoning agents.

The TL;DR
• Role: Internship
• Type: Temporary
• Location: In-person, San Jose, CA

• Mission: To transform front-end designs into silicon, accelerating iteration speed toward final signoff.
• Tech Stack: EDA tooling, SystemVerilog, UVM, Python or another scripting language

What You’ll Actually Do
• Develop: Assist in developing and running Physical Design flows.
• Synthesize: Synthesize digital blocks to meet performance and power targets.
• Automate: Automate final design checks to ensure design integrity.
• Advise: Provide feedback and advise RTL design teams on physical implementation constraints and considerations.
• Improve: Contribute to improving the overall iteration speed from design to silicon signoff.

The Must-Haves
• Background: Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field. Core domain knowledge in high-speed digital logic and ASIC/SoC design principles.
• Experience: Exposure to ASIC or SoC design principles and methodologies; familiarity with hardware description languages like SystemVerilog; familiarity with verification work and the process of writing test benches; familiarity with physical design flows and relevant EDA tooling.
• Skills: Familiarity with high-speed digital logic concepts; ability to learn quickly about transformers and other aspects of modern artificial intelligence; ability to apply physical design flows and relevant EDA tooling.
• Bonus: Familiarity with transformer models and machine learning concepts; familiarity with numerical representations and functions in RTL; familiarity with clocking and reset schemes (both at RTL and Physical Design levels); experience with UVM (Universal Verification Methodology) or formal verification (DV); ability to program with Python or another scripting language.