Chip Package Signal and Power Integrity Engineer
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Job Description
About Google’s Technical Infrastructure Team
Behind every online interaction you have with Google lies the intricate architecture built by the Technical Infrastructure team. This team ensures Google’s product portfolio functions seamlessly, from maintaining data centers to developing next-generation platforms. Their work powers the smooth operation of Google’s services, ensuring users enjoy the best and fastest experience possible.
Job Description: Chip Package Signal and Power Integrity Engineer
Join a diverse team at Google that pushes boundaries and develops custom silicon solutions for the future of Google’s direct-to-consumer products. Contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Chip Package Signal and Power Integrity Engineer, you will be responsible for the chip package design with signal/power integrity simulation and characterization at the chip, package, and system levels. You will be part of a larger team working alongside Chip Architects, ASIC Engineers, Physical Design, and other SI/PI Engineers.
You will collaborate with various cross-functional teams, including:
• Chip Design
• System Design
• Software Team
• Vendors
You will be responsible for driving chip packaging signal and power implementations from product planning to New Product Introduction (NPI).
Responsibilities:
• Contribute to chip-package-system co-design by performing Signal Integrity (SI)/Power Integrity (PI) analysis and optimization. This involves participating in product definition and optimizing chip floorplan, power tree structure, net lists, etc., for High Performance Computing (HPC) based on 2.5D/3D package technology.
• Develop next-generation IO interfaces (serdes, memory, D2D) considering IO PHY, SI/PI, and physical design.
• Collaborate with chip design, system design teams, and suppliers to drive chip package SI/PI design targets, push the boundaries of chip performance, and explore SI/PI and DFM tradeoffs for advanced package design closure for production.
• Provide feedback on chip floorplan considering IP performance/package/system routability and SI/PI.
• Conduct post silicon validation and qualification of high-speed interface for NPI.
Compensation:
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. This range reflects the minimum and maximum target salaries for the position across all US locations. Individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Minimum Qualifications:
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of industry experience in the SI/PI field.
• Experience in chip package SI/PI design for interconnections and advanced package design.
Preferred Qualifications:
• Experience in post silicon correlation with models.
• Experience with 2.5D/3D package design such as silicon interposer, silicon bridge, 3D die stacking.
• Experience in cross-functional collaboration with chip top design, physical design, STA, package, system design, and validation teams.
• Experience in programming and data analysis with Matlab, Python, C++, and statistical tools to establish automation flows and data processing.
• Understanding of on and off chip power delivery and STA/voltage budget.
• Familiarity with memory testing, next generation memory, chiplet standards, and timing budget methodology.
Google is proud to be an equal opportunity and affirmative action employer. They are committed to building a diverse workforce and creating a culture of belonging for everyone.
