CAD Engineering Intern

Job Description

CAD Engineering Intern | Rambus

The Tone:
This is an internship at Rambus, located in San Jose, CA (Hybrid). Rambus is a premier chip and silicon IP provider, creating industry-leading memory interface chips and Silicon IP that advance data center connectivity and solve bottlenecks between memory and processing. This role is crucial for joining a team of bright inventors and engineers to develop products that ensure data is faster and safer, powering advanced chip design and verification workflows. You will contribute to a global team supporting EDA software, infrastructure, design flows, and automation for cutting-edge product chip designs.

The TL;DR
• Role: Internship
• Location: San Jose, CA (Hybrid)

• Team: Central CAD Team | Reports to Director of CAD
• Mission: Develop and support CAD tools, flows, and methodologies to enhance chip design and verification workflows globally, enabling high design productivity and efficient resource use.
• Tech Stack: Python, Tcl, Shell, Perl, IBM LSF job scheduler, Synopsys, Cadence, Siemens

What You’ll Actually Do
• Develop automation: Develop and support software utilities and automation, leveraging Python, Tcl, or Shell, to significantly improve compute job throughput, turnaround time (TAT), and overall compute efficiency.
• Optimize job scheduling: Utilize the IBM LSF job scheduler to actively support and optimize job scheduling operations across both on-premise data center and compute cloud environments.
• Analyze EDA license usage: Work on detailed electronic design automation (EDA) software license usage analysis and optimization, focusing on improving license sharing efficiency and reducing tool contention within a shared global environment.
• Monitor infrastructure metrics: Assist with continuous monitoring, reporting, and in-depth analysis of critical infrastructure metrics, including LSF job queue wait time, run time, resource utilization, and license consumption.
• Collaborate on solutions: Collaborate effectively with CAD, IT, design, and verification teams to identify infrastructure bottlenecks and proactively help develop scalable and efficient solutions.

The Must-Haves
• Background: Minimum qualification is Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related field, with a basic understanding of semiconductor chip design and verification workflows gained through coursework, academic projects, or internships.
• Experience: Strong hands-on software development and automation experience, demonstrated by writing high-quality, maintainable code using Python (preferred), Tcl, Shell, or Perl.
• Skills: Familiarity with Linux/Unix environments, exposure to electronic design automation (EDA) tools from vendors like Synopsys, Cadence, or Siemens, strong analytical and problem-solving skills, and good communication skills.
• Bonus: Interest in compute infrastructure, job scheduling, or shared resource environments, including concepts like throughput, turnaround time, and utilization.