CAD Engineer – Custom Design Automation

Job Description

Technical Staff Engineer – CAD | Microchip Technology

The Tone:
This is a full-time role at Microchip Technology, located in Not specified. Microchip Technology designs the technology that powers the world around us, focusing on state-of-the-art next-generation FPGA devices with RiscV CPUs and full SOC functionality. This role is crucial for ensuring that the company’s design flows and tools for these advanced technologies are robust, reliable, and continuously supported.

The TL;DR
• Role: Full Time
• Location: Not specified
• Mission: Ensure Microchip’s design flows and tools are robust and reliable for state-of-the-art next-generation FPGA devices.
• Tech Stack: Cadence Virtuoso 12, Cadence Virtuoso Studio IC 23.1, Mentor Calibre, SKILL, Perl, Python, CDL, hspiceD, Verilog, Cadence VXL, LSF, DesignSync, AI tools.

What You’ll Actually Do
• CAD Environment Management: Manage industry-standard CAD activities for state-of-the-art next-generation Microchip FPGA devices, which include RiscV CPUs and associated functions for true SOC functionality.
• Design Flow Reliability: Work closely with Microchip teams such as Engineering Services, Design teams, and Operations to ensure that Microchip’s design flows and tools are robust and reliable.
• Technical Support & Vendor Liaison: Provide front-line support for Microchip staff in the use of these tools and flows, and act as an interface with external tool vendors and suppliers to resolve issues and provide guidance as needed.
• Automation & Development: Develop, test, and release custom scripts and tools using SKILL, Perl, and Python to aid in analog design automation, including netlisting customizations for CDL, hspiceD, and Verilog.
• Physical Verification & Tape-out Support: Contribute expertise in writing DRC/LVS runsets for Physical verification flows using Mentor Calibre, and support with or be involved in tape-out activities and foundry interface.

The Must-Haves
• Background: Bachelor’s (BSEE) or Master’s (MSEE) degree with a focus on electrical engineering or a related field.
• Experience: 12+ years of relevant work experience, demonstrating in-depth expertise with setting up Cadence full-custom design environments (including Virtuoso 12, Virtuoso Studio IC 23.1 and above). This includes a strong understanding of 12nm and lower process technologies, such as FinFet, handling standard cell libraries and PDK installations, and managing Pcell creation, debugging, and migration flows. Proven track record in writing DRC/LVS runsets for physical verification flows using Mentor Calibre, and experience with CDL, hspiceD, and Verilog netlisting customizations. Expertise in setting up and debugging LSF/DesignSync issues.
• Skills: Expertise in SKILL, Perl, and Python scripting for design automation; proficiency in debugging AMS/Custom Design EDA tool issues; in-depth knowledge of Cadence VXL; ability to setup and debug LSF/DesignSync issues; strong communication skills for coordinating tasks across global sites.
• Bonus: Experience in using AI tools to speed up deliverables.