• University: Texas Tech University
• College: Texas Tech University
• Major: Electronics and Communications Engineering (VLSI)
• Minors: NA
• Start Date: 25 August 2023

Physical Design Engineer

Optimized pipelining flops to enhance placement efficiency and minimize timing violations. Conducted floorplan experiments that improved the quality of results (QOR) and mitigated clock latency challenges. Executed Place and Route (PnR), Static Timing Analysis (STA), and Design Rule Check (DRC) fixes, achieving block-level timing closure and DRC clean signoff. Employed skew techniques to resolve critical setup and hold timing violations. Managed a 1.5M cell partition comprising 109 macros, refining placement to reduce congestion. Delivered RTL feedback on unlocked registers, timing loops, and unconstrained endpoints, significantly enhancing design accuracy.

Graduate Assistant

Facilitated student understanding of solid-state devices, integrated circuit (IC) design, and physical design principles. Conducted laboratory sessions emphasizing IC layout design, timing optimization, and DRC/LVS verification.

• LGBTQ: no
• Ethnicity: Asian
• Disability: no
• Veteran: no
• First-generation College Student: no
• Pell Grant Eligibility: no
• Work Authorization: yes
• Visa Sponsorship: yes