Design Verification Engineer
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Job Description
About the company:
Google is a global technology company that specializes in Internet-related services and products, including search, cloud computing, software, and hardware. It is one of the largest and most well-known companies in the world.
About the job:
The Design Verification Engineer position at Google is responsible for planning and executing the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP. This includes creating and enhancing constrained-random verification environments using SystemVerilog and UVM, or formally verifying designs with SVA and industry leading formal tools. The ideal candidate will have a Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience, as well as 2 years of experience working with digital logic at RTL level using System Verilog or C/C++. Preferred qualifications include a Master’s degree or PhD in Electrical Engineering or Computer Science, experience with Interconnect Protocols (e.g., ACE, CHI, CCIX, CXL), experience with building verification methodologies that span simulation, emulation, and FPGA prototypes, and Architectural Experience in one or more of the following: Operating Systems, Memory Management, Caches Hierarchies, Coherency.
